IP 组合
XinSiYuan Mixed Signal IP

VeriSilicon cooperates with Synopsys to provide XinSiYuan mature analog IP for 40nm above process. Those Tier1 mixed signal IP portfolio consists of hundreds functional “building blocks” specifically designed for most industry’s popular process technology, ranging from 0.18um to 40nm. These SIP (semiconductor IP) blocks offer ease of integration and verification – providing reliability, risk reduction and time-to-market advantages in the development of complex SoCs and ASICs. Silicon proven and production proven are key indicators of IP quality that demonstrates VeriSilicon’s commitment to customer success.

  • ADC
  • DAC
  • DDR
  • HDMI
  • MIPI
  • USB
  • PCIe
  • SATA
  • XAUI

Register today for request XinSiYuan’s analog IP.