IP 组合

VeriSilicon Universal Compression Solution

VeriSilicon Universal Compression IP is developed to remove system bottlenecks in SoC data communications as a result of ever-increasing functionalities, bandwidth consumption, and screen resolution. The numbers of processing elements inside the SoC that need to share system resources can include the CPU, GPU, VPU, DSP, ISP, Vision, DC, and sensors, leading to huge amounts of pixel (visual) data and bandwidth that need to be processed and moved around. Building massive DDR and bus bandwidth are not practical nor cost-effective. Having compression solution in such complex SoC is no longer a question, but it is a must-have.

However, most compression solution offered in the industry today only works with IPs from the same supplier. This limits SoC design significantly and hinders building differentiated product offering. VeriSilicon’s compression solution not only offers the best compression ratio and works with VeriSilicon IPs, but it also works with other supplier’s IPs.

VS Universal Compression Data

The DEC400 Universal Compression IP is at its 4th generation today.
It offers the following configuration and supports to adopt to wide range of SoC applications.

  • DEC400 embedded inside VeriSilicon Graphics, Video, Display IPs.
  • Bayer formats (8-bit, 10-bit, 12-bit) in raster pattern: commonly used in MIPI interface and ISP engine.
  • YUV 420 and 422 formats (8-bit and 10-bit components) in raster and tile patterns: commonly used in ISP and Video Codec.
  • RGB 16bpp and 32bpp in various tile patterns: commonly used in graphics.

VeriSilicon operates worldwide and is happy to meet with you to discuss your compression needs anytime you want.
Simply reach out to your nearest VeriSilicon sales office and schedule a meeting or meet with us at the next supported industry event!