平台化芯片设计服务
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SiP 服务

VeriSilicon has advanced SiP (System in Package) assembly technology, testing methodology, and has set up an established SiP eco-system. The advantages of this service are our ability to provide customized differentiated products with smaller form factor, better electrical performance, lower power consumption, faster time to market and cost competitive SiP turn-key service.

  • SiP technical proposal and cost estimation
  • The third party KGD (known good die) purchase and management
  • Passive components purchase and management
  • Package design and chip-package-PCB co-design/co-simulation
  • Design for testing, test plan and test program development
  • SLT (system level testing)
  • Reliability qualification service
  • Debug/failure analysis
  • Domestic/overseas logistics operation
  • Fast time to market
  • Continuously cost down solution.
  • Flexible business cooperation.

SiP Design Flow